A specific MCU design of On board Unit (OBU) in Electronic Toll Collection (ETC) system is proposed in this paper. According to the ETC applications, this MCU is designed to have the minimum application system. Results show that this MCU design scheme is feasible and fulfills the requirements of the central control chip used for OBU in ETC system. The MCU has about 113,000 gates, and its area is 642.74 !-lm x 494.20 !-lm under SMIC 65nm technology. The average power consumption is 98!-lW. Compared with the general MCU, the MCU has a larger advantage in ETC application.
With the widespread application of ETC system, the development of OBU device becomes a hotspot of intelligent transport systems . Currently on the market, OBU device is realized by using the method of board level circuit . The device has bulky appearance, high cost, and is not conducive to the promotion of a wide range. As shown in Figure 1, SOC is a viable solution to solve this shortcoming. Reader chip (13.56MHz)
Soft IP core has advantages of low cost, free configuration, and it can be embedded into other function module. Therefore, IP soft core becomes the main part of SOC design . ARM processor has excellent performance, but its power consumption is very low and the number of gates used is small . In this design, a 32 bit RISC processor IP core designed by ARM company is used. CHIP DESIGN System Design The overall design of the system: The final design is applied to the OBU in ETC system. The MCU is able to control 5.8G RF chip and 13.56M reader chip, and communicates with them. ARM IP core is used as the CPU core. SPI, UART and other interfaces are designed as peripheral. The control signal and interrupt signal of 5.8G RF chip and 13.56M reader chip are also required. The system clock is designed as 55MHz. The chip system block diagram is as follows:
Taking into account the application and scalability of the design, the SRAM is designed as 8 k bytes. Second, the program of CPU is stored in the ROM and EFLASH. The bootloader, the interface used for program download, the drivers of peripheral interfaces and the drivers of EFLASH operation are stored in ROM. By assessing the amount of the program, the capacity of the ROM is designed as 2 K bytes. The main application program is stored in EFLASH. According to the amount of actual application code, taking into account the scalability of chip design, an EFLASH with 64 k bytes is used in the design. Module division: The memory management unit: ROM, SRAM and EFLASH connect with CPU through AHB. Through the logical address, the CPU accesses different memory areas. So this design achieves the memory management unit as an interface of CPU bus and memory IP to realize the ICSICT2014, Guilin, China
function of mapping the logical address to physical address and the function of timing conversion. This design can realize unified management and access, and facilitate the extension of memory in the future. The interface module: In order to communicate with peripheral chips, two SPI masters and a SPI slave are designed. They are used to communicate with the 5.8G RF chip and 13.56M card reader chip. In addition, in order to meet the requirements of peripheral chips, a group of GPIO and 4 interrupt interfaces are designed. Chip needs the entrance to download program and other application interface, so two UART interfaces are designed to download the program and meet other application. These interfaces are connected to CPU through APB. Clock and reset module: The chip needs a 55MHZ system clock which is provided by an external crystal oscillator. The design of the reset module combines synchronous reset and asynchronous reset. The reset signal after synchronization is used to asynchronous reset. The clock module divides the system clock generated by analog circuit to produce the desired clock after gating, reducing the power consumption of the chip. Memory Management Unit Design The memory management unit is connected with CPU and memory module.
The CPU can access the memory via the AHB bus. ROM IF, EEPROM IF, and EFLASH Controller are control modules of ROM, RAM, and EFLASH. Particularly, EFLASH Controller also connects with the APB bus, which is the channel for UART interface to download the program to EFLASH. MMU
The function of decoder is to map the logical address to a physical address, and produce memory chip select logic. The address assignment is shown in
The SPI master implementation process is as follows: Generally, SPI is in sleep mode. When SPI master is in sending mode, CPU configures the registers of SPI master. First, CPU configures control register, baud rate register, and byte register. Then, CPU configures data register, and SPI master enters the sending state. In the sending state, the data in data register is first loaded into the shift register. At the same time CS signal and SCLK signal are outputted according to the baud rate register. Finally, the shift register is shifted, and the highest bit is outputted as MOSI based on the edge of SCLK. When SPI master is in receiving mode, the CS signal is still valid. According to the edge of SCLK, the received data is loaded into shift register. Once SPI master receives a byte of data, CPU takes the data away, and then SPI master continues to accept the next byte signal. SPI slave, UART, GPIO, and interrupt interfaces are not elaborate in this paper. By using clock gating technique, the clock signals of these modules are pulled up when these modules are not in use.
Function Simulation The design verification includes memory operation and interface protocol. This design uses Verilog HDL to write RTL code and build a test platform. Verification platform contains memory model, SPI master model, SPI slave model, and UART model. The function verification is based on Cadence simulation tool NC-Verilog. The method of Hardware Software Co-design is used to verify the function of each module. All kinds of operation are performed using bootloader, driver and application program. Program is loaded into memory model by $readmemh or $readmemb command. Figure 4 is the function simulation results of memories and peripheral interfaces. The timing of these modules meets the requirements of the specification, and signals are correct compared with the expectation.
The design verification plan is divided into the following stages: First, the UART interface is tested. The program download interface which is cured in ROM is used to test UART interface in this design. Since the UART interface can be used to observe the intuitive behavior and internal data, so it is used to test other modules. Then, EFLASH is tested. Chip download function is tested by constantly writing data to the EFLASH program area through UART interface and verifying the correctness while downloading. After this test, EFLASH can download program used to Hardware Software Co-verification. This facilitates the subsequent verification. Finally, the SPI interface is tested. The SPI interface is tested through communicating with 13.56M reader chip and 5.8G RF chip which are high reliability chips. After that, the GPIO and other function modules are also tested. The results of FPGA verification show that the design meets the function requirements of OBU in ETC system.
CONCLUSION This paper completes the specific MCU of OBU in ETC. The chip successfully integrates ARM IP core, ROM, SRAM, EFLASH, MMU, SPI master, SPI slave, UART, GPIO, and interrupt interfaces. By successfully implementing the minimum application system and using clock gating technique, the characteristics of central control chip of OBU in ETC are realized. Results show that the MCU only has about 113,000 gates, occupies 642.74fill1 x 494.20 fill1 area, and consumes on average 98!! W power under SMIC 65nm technology. Compared with the general MCU, this MCU has a significant advantage and lays a good foundation for further development of the theory and Practice for OBU in ETC.